Tuesday, 23 April 2013

Xilinx ISE 12.4 Hello world example on nexys3 board

 This is a tutorial for using Xilinx ISE 12.4.

In this tutorial you will learn:
  ·         How to create a new project
  ·         How to add new files to your projects
  ·         How to create a test bench for your project
  ·         How to create a constrain file.
  ·         How to create a “.bit” file for your FPGA.
  ·         And how to program the FPGA.

Note: This tutorial is targeting nexys3 board only. It can be used on other boards but another “.ucf” file is required.

This tutorial assumes you have a previous knowledge of Verilog programming language.

Creating a project
  ·         Open the new project wizard  by clicking on File->New Project
  ·         Write your project name and choose its location, in this tutorial the project name is “HelloWorld”, and click next
  ·         In this window you choose the FPGA family and device, the preferred language, the simulator and the synthesis tool. For this tutorial:
  o   Family : Spartan6
  o   Device: XC6SLX15
  o   Package: CSG324
  o   Synthesis tool: XST(VHDL/Verilog)
  o   Simulator: ISim(VHDL/Verilog)
  o   Preferred language: Verilog
  ·         Keep the rest as it is and click next then finish.

  
Adding files to project
You can create new file for the project or use an existing file or copy an existing file. In this tutorial we will create new files.
  ·         Click on Project->New Source
  ·         Select Verilog Module then write the file name, “helloword_top”, then click next.
  ·         Here you can add ports to the module you are creating. You can choose if its input port, output port or inout port. If it is more than one bit you make “Bus” checked and specify the most significant bit and the least significant bit. This is optional, I don’t use it usually I like to write the ports myself so we will leave it empty and click next and finish.

The Hello World Example
          In this example we will use a button and a switch to control to LEDs.
            So we have two inputs: button, switch.
            And two outputs: LED_B, LED_S.
Write the following in the helloworld_top file:
////////////////////////////////////////////////////////////////////
module helloworld_top(input Button,input Switch,output LED_B,output LED_S);
           
             assign LED_B = Button;
             assign LED_S = Switch;

endmodule
////////////////////////////////////////////////////////////////////
To implement the module go to Process-> Implement Top Module.

Creating Test Bench
Test bench is used to test the module on simulator. The test bench is a module with no inputs or outputs and it contain the module you want to apply the test on.
To create a test bench:
  ·         Click Project->New Source.
  ·         Select Verilog Test Fixture then write the name of the file “helloworld_top_tb” then click next.
  ·         Now choose the module you want to include in this test bench which is the only one we have here “helloworld_top” and click next and finish.
  ·         Write the following in the “helloword_top_tb”
////////////////////////////////////////////////////////
module helloworld_top_tb;
            reg Button;
            reg Switch;
            wire LED_B;
            wire LED_S;

            helloworld_top uut (
                        .Button(Button),
                        .Switch(Switch),
                        .LED_B(LED_B),
                        .LED_S(LED_S)
            );

            initial begin
                        Button = 0;
                        Switch = 0;
                        Button = 0;
                        Switch = 0;
                        #10;
                        Button = 1;
                        #10;
                        Switch = 1;
                        Button = 0;
                        #10;
                        Button = 1;
                        #10;
                        Switch = 0;
                        #10;
                        Button = 0;
                        #10;
            end     
endmodule
////////////////////////////////////////////////////////
  ·         To run the simulation you have first to change the design view from “implementation” to “simulation”. Its radio buttons in the upper left side.
  ·         Then select the “hellow_top_tb” file from the hierarchy window on left.
  ·         Now in the lower window double click Simulate Behavioral Model.
  ·         The simulator will start and signals will appear.
  ·         To get full view of the simulation go to View->Zoom->To Full View.
  ·         You should have something similar to img1.
  ·         To adjust the simulation time, in the ISE right click on Simulate Behavioral Model then choose process properties then adjust the “simulation run time”. I am using 1000 ns.


img1


Creating Constraints file
The constraints file is used to define the clock(s) frequencies and to map the ports to FPGA pins.
  ·         First return to “implementation” view.
  ·         To create a constraints file click Project->New Source.
  ·         Select implementation constraints file and write the name of the file “helloworld_top” then click next and finish.
  ·         We will use the down button and the most right switch with the two most right LEDs.
  ·         Add the following to the constraints file
////////////////////////////////////////////////////////
NET "Button" LOC = C9;
NET "Switch" LOC = T10;
NET "LED_B" LOC = V16;
NET "LED_S" LOC = U16;
////////////////////////////////////////////////////////

Creating “.bit” file
  ·         Select the Verilog file “helloworld_top” from the hierarchy window and from the lower window double click Generate Programming file.

Programming the FPGA
  ·         We can use Xilinx iMPACT or Digilent Adept software. We will use the last one.
  ·         Connect the FPGA to the PC using the Digilent Adept USB port.
  ·         Run the Digilent Adept software.
  ·         Click Initialize Chain.
  ·         In the FPGA line, click Browse and select the “helloworld.bit” file from the project directory.
  ·         Click Program.

After programming the DONE led on the board will light and you can test the work :)

4 comments:

Neolithic said...

This is very nice sir, I have the same board you used to show the test. I would like to see some more examples from you on this. Thankyou.

Neolithic said...

And i have a question for you on this:
Question: In the following Code snippet

initial begin
Button = 0;
Switch = 0;
Button = 0;
Switch = 0;
#10;
Button = 1;
#10;
Switch = 1;
Button = 0;
#10;
Button = 1;
#10;
Switch = 0;
#10;
Button = 0;
#10;
end

you have not applied any condition to check if a certain switch is 1 then LED_B or LED_S turns on. and there is no command explicitly turning on and turning off LED in test bench. Can you please tell me about it.

Regards:
Junaid Aslam

Unknown said...

Hi Junaid Aslam,

Thanks for your comments :)

This is a test bench where you test the module functionality.
Its a testing scenario, a sequence of inputs with delays to test the module behavior.

The conditions type you mentioned can be used in creating the module it self. In test bench i think you can check if an output signal occurred to change another input.
In VHDL you can ether use conditions or delays in a test bench but i don't know about verilog, i just made this example for someone who asked for it :)

Also i don't have the kit so please tell me if the example is really working.

I can make more examples in my process of learning verilog. i know VHDL but i want to learn verilog also :)

Neolithic said...

Sure sir, i shall soon test your code and will let you know if it works. In addition i will also tell you if i make any amendments to make it work. I want to learn verilog too, but i don`t know VHDL either. Can you please teach me VHDL a little, because i have heard that in complex designs VHDL is much better. what is your opinion?